1. In the Energy Storage Business, Efficiency Is Money

The business model of a battery energy storage station is disarmingly simple: charge at off-peak rates, discharge at peak rates, and profit from the spread — with revenue scaled by cycle count. For a commercial and industrial (C&I) energy storage station designed around two charge-discharge cycles per day over a service life exceeding fifteen years, every percentage point of efficiency loss is multiplied thousands of times over by those cycles. Industry estimates consistently indicate that a 1% improvement in power conversion system (PCS) efficiency can increase the lifetime revenue of a storage system by 5% to 8%. As the only power path between the battery bank and the grid, the bidirectional conversion efficiency of the PCS directly determines whether the economics of the project close.

The industry‘s answer has converged in recent years: replace silicon IGBTs in the power stage with silicon carbide. Published field measurements show that a three-level C&I storage PCS built with 1200V SiC MOSFETs can achieve peak efficiency above 98.8% — roughly one percentage point higher than comparable IGBT designs, along with a 20% to 25% improvement in power density. Using the HuaXuanYang Electronics HXYS120N120MPI (1200V / 120A / 16mΩ in a Kelvin-source TO-247H-4L package) as the reference device, this article walks through the selection logic for the bidirectional bridge legs of an 800V-bus C&I storage PCS, along with several design pitfalls worth avoiding.

2. Why an 800V Bus Makes the PCS Difficult

The DC bus of a C&I storage battery system typically operates between 600V and 900V, with 800V as the most common nominal operating point. This voltage range is unkind to power devices, and the pain points concentrate in three areas.

First, the efficiency ceiling. A conventional two-level IGBT design limits switching frequency to roughly 2 to 10kHz; pushing beyond that makes switching losses and current-tail behavior unmanageable. Low switching frequency forces bulky boost and output filter inductors, which lock in the size, magnetics cost, and copper losses of a 100kW-class power stage. After peak efficiency reaches 97% to 98%, every additional 0.1 point demands disproportionate effort.

Second, voltage stress sits close to device limits. In a two-level topology, each switch must block the full DC bus voltage plus turn-off overshoot and grid transients. Applying the standard engineering margin of 1.5x, an 800V bus calls for devices rated at least 1200V — and IGBTs at that voltage class have even poorer switching characteristics, compounding the problem.

Third, the dual test of bidirectional operation and grid-forming control. A modern PCS is no longer merely an inverter: it rectifies while charging, inverts while discharging, and provides four-quadrant reactive power support. As renewable penetration rises, grid-forming (GFM) control demands millisecond-level power response and wider control bandwidth. A low switching frequency caps the achievable control-loop bandwidth, which increasingly disadvantages IGBT-based designs.

3. Placing 1200V SiC on an 800V Bus: The Numbers

The HuaXuanYang HXYS120N120MPI is an N-channel SiC MOSFET intended for high-voltage, high-frequency power stages. Four key parameters map directly onto the three pain points above.

1200V rating: a 1.5x margin for the 800V bus. In both two-level and T-type three-level topologies, the main switches of each bridge leg block the full bus voltage. A 1200V device on an 800V bus retains sufficient margin for turn-off overshoot, bus pumping, and grid transients, without compromising switching performance for the sake of voltage rating.

16mΩ on-resistance: conduction losses that IGBTs cannot approach. Take a 60kW three-phase 400Vac unit: phase current is approximately 87A RMS, and each device, conducting a sinusoidal half-cycle per fundamental period, carries roughly 60A RMS. At 16mΩ (25°C), per-device conduction loss is about 60W; factoring in an estimated 1.4x resistance increase at elevated junction temperature, loss remains around 80W — comfortably manageable in practice. By comparison, a 1200V IGBT at the same current level incurs noticeably higher combined conduction and tail-current losses, which is one of the main contributors to the roughly one-point efficiency gap. Actual losses should be confirmed against the datasheet and system-level measurements.

120A current rating: one device per position covers 60kW-class designs; paralleling covers 100kW and beyond. Following the common engineering practice of keeping continuous current below half of the device ID, a single-device design fits a 60kW-class three-phase PCS. At 100 to 125kW, two devices in parallel per switch position carry about 55A RMS each, still preserving roughly a two-fold margin. Current sharing in paralleled devices deserves attention and is addressed in the design notes below.

TO-247H-4L Kelvin package: unlocking SiC switching speed. The value of SiC lies not in conduction but in switching. In a conventional three-lead TO-247, source lead inductance sits in both the power loop and the gate loop; as switching speeds rise, the induced voltage across that inductance opposes the gate drive, and Miller-induced false turn-on becomes a real risk. The TO-247H-4L brings out a dedicated Kelvin source lead, decoupling the drive loop from the power loop. False turn-on caused by high dv/dt is substantially suppressed and gate ringing converges more easily — meaning the device can confidently operate at 20 to 50kHz instead of being dragged back to IGBT-era speeds by its package.

Taken together, these four parameters point to a single conclusion: roughly one percentage point of efficiency gain, several times higher switching frequency, a 30% to 50% reduction in filter and magnetics volume (partly attributable to the three-level topology itself), and a 20% to 25% improvement in power density — the system-level benefits that published industry estimates attribute to SiC relative to IGBT designs.

4. Reference Circuit: Building the T-Type Three-Level Bidirectional Bridge Leg

For C&I storage PCS in the 60 to 250kW range, three-level topologies dominate, and the T-type three-level (TNPC) is a common landing point for the 800V-bus-plus-1200V-SiC combination thanks to its low device count and short conduction path.

Main power loop (textual description, single phase): The DC bus is established by the battery side, either directly or through a DC-DC stage. Bus capacitors Cbus1 and Cbus2 are connected in series with their midpoint O brought out. Each phase leg contains four switches: T1 connects the positive bus P to the AC output point A; T2 connects A to the negative bus N; and T3 and T4, connected in anti-series, link A to the midpoint O. The output takes three levels — +Udc/2, 0, and -Udc/2. During the positive half-cycle, T1 chops at high frequency; near the zero crossing, T3 and T4 conduct and clamp the output to the midpoint; during the negative half-cycle, T2 chops at high frequency. Three phase legs share the DC bus and connect to the grid through an LCL filter.

Bidirectional operation requires no additional hardware. In discharge mode, the legs operate as an inverter, transferring energy from battery to grid. In charge mode, the same legs operate as a PWM rectifier with energy flowing the opposite way, with power factor and current waveform quality both managed by the control algorithm. This is where SiC‘s high switching frequency pays off: charge-discharge transitions can be made smooth and seamless, compressing transient time to the millisecond level required by grid-forming applications.

Bill of materials and device placement rationale (100 to 125kW example):

The mixed bill of materials — 1200V at the high-frequency positions and 750V at the clamp positions — is an industry-proven cost optimization: the clamp switches see only half the bus voltage and need not be 1200V devices, while 750V parts can achieve lower on-resistance, benefiting both system cost and efficiency.

System-level signal chain: The control layer, implemented on a DSP or dedicated digital controller, samples grid voltage, grid current, bus voltage, and midpoint potential; executes SVPWM modulation and midpoint-potential-balancing algorithms; and manages charge-discharge transitions along with grid-forming control logic. The drive layer uses electrically isolated SiC gate drivers — typically +18V for turn-on and -3V to -5V for turn-off to counter the Miller effect — with propagation-delay matching between the two drive paths (within tens of nanoseconds) and integrated desaturation detection with soft turn-off protection. The power layer is the SiC bridge leg described above, with external gate resistors typically in the range of a few ohms to just over ten ohms to balance switching speed, ringing, and EMI. At the load and grid level, the LCL filter attenuates the 20 to 50kHz switching ripple to within grid-code limits, while on the battery side, bus ripple current and its effect on battery lifetime deserve attention. The four layers interlock: the control algorithm generates the switching sequence, the gate drivers determine whether the devices execute it faithfully, device switching characteristics determine how small the filter can be, and the outcome lands on power quality and overall efficiency. The values cited here are order-of-magnitude references; final decisions belong to the datasheet and bench measurements.

5. Design Pitfalls and Practical Guidance

First, negative-voltage turn-off is not optional — it is mandatory. SiC switching produces high dv/dt, and the coupled Miller current is sufficient to force a device on when it is held at 0V, causing shoot-through. Recommendation: apply a -3V to -5V turn-off level, paired with Miller clamping or a sufficiently low-impedance turn-off loop; evaluate drive-supply ripple separately on high-dv/dt legs.

Second, keep the Kelvin source connection shorter than everything else. The fourth lead of the TO-247H-4L is a drive-dedicated Kelvin source. It must return to the driver‘s reference ground as directly as possible — never share copper with the high-current power ground. If the Kelvin trace loops back into the power ground, the benefit of the four-lead package is voided entirely. Recommendation: keep driver ground-to-Kelvin-pin distance at the millimeter level and minimize the drive loop area.

Third, dead time can be short, but set it from measurements. SiC dead time can shrink to the 100–200ns range, which is key to reducing waveform distortion and reclaiming effective duty cycle in a three-level leg. But the value must be set from measured switching delays, not copied from a reference design. Recommendation: start from twice the datasheet typical delay, verify the absence of shoot-through with a double-pulse test, then tighten.

Fourth, treat midpoint balancing as a control problem, not a hardware afterthought. The midpoint potential of a three-level leg drifts with charge-discharge state, modulation index, and load power factor. Once it drifts, clamp-switch voltage stress becomes asymmetric and the bus capacitors suffer. Recommendation: implement midpoint balancing via redundant small-vector allocation within SVPWM, and keep bus capacitor values and balancing resistor networks symmetric in hardware.

Fifth, achieve paralleled current sharing through layout, not post-hoc tuning. In 100kW-plus designs with two devices per position, sharing is determined by the symmetry of each parallel position‘s loop impedance. Recommendation: mirror the power and gate loops of the two paralleled devices, route independent Kelvin returns and individual gate resistors, and only then assess thermal coupling.

Sixth, design short-circuit protection on SiC‘s timetable. SiC devices tolerate short-circuit conditions for far less time than IGBTs; conventional slow overcurrent logic cannot keep up. Recommendation: implement a fast protection path with desaturation detection and soft turn-off — lowering the gate gradually upon fault detection rather than hard-switching off, which would slam an overvoltage spike across stray inductance.

6. Closing Perspective

For an 800V-bus C&I storage PCS, the selection logic reduces to one thread: use 1200V SiC to get efficiency, frequency, and power density right in the same design. The HuaXuanYang Electronics HXYS120N120MPI (1200V / 120A / 16mΩ, TO-247H-4L) covers single-device 60kW-class designs as well as paralleled configurations above 100kW, and pairs with the HXYS153N75L (750V / 153A / 11mΩ) at the clamp positions in a mixed bill of materials — a complete device selection path for storage and inverter manufacturers transitioning from discrete designs toward power modules. As a company focused on advanced power semiconductors, HuaXuanYang Electronics continues to invest in SiC MOSFETs and SiC diodes, serving high-voltage, high-frequency photovoltaic and energy storage applications with devices validated under demanding operating conditions. For selection details and sample requests, contact HuaXuanYang Electronics.

The content of this article is for reference only and does not constitute any purchasing or design commitment. For design selection, please refer to the latest official HuaXuanYang datasheets. For application-specific questions, contact HuaXuanYang technical support (sales@hxymos.com).