I. The Missing 0.3% Hides in 100 Nanoseconds

A server power supply fails its full-load burn-in test by a hair: overall efficiency lands at 97.2%, while the ORV3 specification draws the line at 97.5%. Swapping in a MOSFET with lower on-resistance claws back only 0.1%. The rest of the gap shows up on the oscilloscope, staring at the half-bridge switching node: the dead time was set to 300 ns, and the body diodes burn a slice of energy every single switching cycle. Dead time in an LLC converter is, at its core, an energy ledger. Whether the switch can take the voltage and how low its on-resistance sits certainly matter — but how those few hundred nanoseconds are budgeted decides whether zero-voltage switching (ZVS) is actually delivered, and how many watts the body diode burns for free.

II. What the Dead-Time Ledger Is Actually Accounting For

The way the LLC primary side switches makes dead time special: turn-on is ZVS, but turn-off is a hard switching event carrying the magnetizing current. Between the turn-off of the upper switch and the turn-on of the lower one, the resonant current has to accomplish two things in sequence. First, it charges and discharges the parasitic capacitance at the switching node — the output capacitances Coss of both switches — until the drain-source voltage of the incoming device resonates down to zero. Second, after the current reverses, it freewheels through the body diode while waiting for the gate drive to arrive. How long each of these two steps takes is the very substance of the dead-time ledger.

Entry one: the body-diode bill when dead time runs long. If the window is longer than the resonant commutation actually needs, the surplus time conducts the entire magnetizing current through the body diode. A silicon MOSFET body diode drops less than 1 V; a SiC MOSFET body diode typically drops in the range of 3 to 4.5 V (consult the datasheet for exact values). With the same magnetizing current flowing, every extra nanosecond is billed. Using the engineering estimate P = 2 × VSD × Im × t_dead × fsw (two commutations per cycle for a half-bridge) and a magnetizing peak current of 1.5 A: at 200 kHz, a 300 ns dead time corresponds to roughly 0.6 W of body-diode loss; push the frequency to 500 kHz and the same dead time burns about 1.6 W. The higher you go in frequency, the faster this entry compounds.

Entry two: the hard-switching bill when dead time runs short. If the window is too narrow, the charge on Coss is not fully removed and the gate command arrives before the drain-source voltage has resonated to zero. Hard turn-on brings back the full voltage-current overlap loss, and the bridge leg can even fall into the capacitive mode, where the resonant tank pushes current back into the bus. That forfeits the entire soft-switching dividend of the LLC, and it is one of the classic device-failure paths during LLC debugging.

Entry three: the insufficient-magnetizing-current bill at light load. As the load falls, the resonant current shrinks, and the magnetizing energy may no longer suffice to swing the Coss transition. Lost ZVS at light load, with the efficiency curve sagging at the low end, is a chronic condition of LLC designs.

A silicon superjunction MOSFET makes all three entries hard to settle at once: its output capacitance stores considerable energy and its body diode carries a large reverse-recovery charge Qrr, so the dead time must stretch to 300-500 ns to leave enough room for commutation; and during startup inrush or capacitive-mode hard recovery, the large reverse-recovery current is a frequent root cause of devices lost during bring-up. In a silicon design the dead-time ledger is essentially a losing proposition — you pay whether you set it long or short.

III. SiC Rebalances the Ledger: How HXYS116N65L Converts Its Ratings

Placing a 650 V SiC MOSFET into the LLC half-bridge changes how the ledger is computed. Using the HuaXuanYang Electronics HXYS116N65L as the worked example, here is how its three headline ratings translate into a 3 kW server power supply:

650 V rating — comfortable bus margin. The upstream PFC stage regulates the bus to 400 V, and the half-bridge switching node is structurally clamped near the bus. Including commutation ringing, the device stress sits around 450-550 V, leaving the 650 V class with more than 1.5x margin — the mainstream choice for the LLC stage in server and telecom power. For designs that prioritize reliability headroom, the 750 V class is an available step up (see the comparison table near the end).

RDS(on) = 20 mΩ — conduction loss held to around 2 W. The primary RMS current of a 3 kW LLC is on the order of 10 A, so each switch dissipates P = I² × RDS(on), roughly 2 W — easy to budget in thermal design. SiC devices also exhibit a relatively gentle on-resistance drift with temperature, so full-load case-temperature predictions rarely need rework.

ID = 116 A — more than ten times current headroom. Startup inrush, load transients, and output-short events are all absorbed by specification margin rather than by running the device at its limits.

TOLL surface-mount package — the ticket to high-density layout. Low profile, low parasitics, and compatibility with automated assembly make TOLL the mainstream package for surface-mount LLC stages today; where a through-hole option is preferred, the HXYS108N65MP (650 V / 108 A / 20 mΩ, TO-247) offers the same parameter class in a leaded package.

Yet the entries that truly win the ledger are two device-level characteristics of SiC:

First, the energy stored in the output capacitance (Eoss) is an order of magnitude lower. The physical threshold for ZVS is that the magnetizing energy must be able to sweep the energy stored in the switching-node capacitance at bus voltage. With Eoss down, the threshold current drops, and the magnetizing inductance Lm can be pushed higher — reducing primary-side circulating current so that the 20 mΩ conduction advantage converts fully into system efficiency instead of being consumed by reactive circulation. Industry practice pushes the inductance ratio (Lm/Lr) of SiC LLC designs to 7-12; for fixed-input applications such as server power, 3-7 balances gain and loss.

Second, the body-diode reverse-recovery charge Qrr is small. The dead-time window can be compressed to 50-150 ns without white-knuckle debugging: even if a startup or load-step event momentarily drops the converter out of ZVS, the small reverse-recovery current avoids the violent hard-recovery surge typical of superjunction silicon. Field practice shows SiC designs exhibit strong immunity to capacitive-mode events, allowing relaxed thresholds for anti-capacitive-mode protection and more robust dynamic behavior under disturbed grids and abrupt loads. That is the confidence behind daring to shorten the dead time.

IV. Budgeting Dead Time in the Design Flow: The System-Level Ledger of a Half-Bridge LLC

The ledger only lands when placed in the full circuit. The upstream totem-pole PFC regulates the rectified input to a 400 V bus. In the LLC stage, Q1 and Q2 (HXYS116N65L) form the 400 V half-bridge; the switching node feeds the resonant capacitor Cr in series with the resonant inductance Lr and the transformer primary, with the magnetizing inductance Lm in parallel across the primary winding. On the secondary side, synchronous rectifiers rectify the transformer output, and after output filtering a 12 V high-current rail feeds the server board.

The system-level signal chain runs like this: at the control layer, an LLC controller or DSP generates frequency-modulated PWM with a duty cycle fixed at 50% minus the dead time, adjusting gain through frequency; the digital loop simultaneously implements adaptive dead time and light-load burst mode. At the driver layer, isolated gate drivers deliver +18 V turn-on and -4 to -5 V turn-off rail voltages (a common SiC recommendation; consult the datasheet), with separate turn-on and turn-off gate resistors — the matching of the two channels‘ propagation delays directly determines how symmetric the effective dead time is. At the power layer, the devices execute ZVS turn-on and hard turn-off, with the Miller plateau pacing the voltage transition at the switching node. At the load layer, the secondary synchronous-rectifier timing stays phase-locked to the primary resonant current, and at light load the rectifier timing cooperates with burst mode so that light-load efficiency does not sag.

Dead-time design proceeds in three steps along this chain (all values below are order-of-magnitude references; confirm by measurement):

Step one — the energy check. The energy stored in the magnetizing inductance at turn-off must be able to sweep the energy stored in both switches‘ Coss at bus voltage: 0.5 × Lm × Im(peak)² ≥ 2 × Eoss(400 V). The magnetizing peak current follows Im(peak) = Vin / (4 × fsw × Lm): with a 400 V bus, 200 kHz, and Lm = 0.33 mH, Im comes to about 1.5 A. This step decides how large Lm can be — the SiC solution leverages its low Eoss to push Lm upward, reducing circulating current and primary copper loss together.

Step two — the timing check. The dead-time window must cover the charging/discharging time of the switching-node capacitance, estimated as t_dead ≥ Coss(eq) × Vin / Im, plus 20-30% margin to absorb gate-drive delay, body-diode conduction delay, and resonant-component tolerance.

Step three — compress by measurement. Start from 250 ns. At half and full load, probe the switching-node voltage VSW and the lower switch‘s gate voltage VGS simultaneously: the moment VSW has just resonated to zero while VGS is just crossing the threshold is the dead-time floor. SiC designs typically land in the 80-150 ns range.

Closing the ledger: cutting the dead time from 300 ns to 100 ns saves about 0.4 W of body-diode loss directly at 200 kHz; at 500 kHz the direct-loss gap widens beyond 1 W. The larger gain sits in the hidden entries: at 200 kHz a 300 ns dead time consumes 12% of each half-cycle, while at 500 kHz the same 300 ns consumes 30%. Compressing to 100 ns restores the effective duty cycle from about 70% to about 90%, pulling down primary RMS current, transformer copper loss, and body-diode conduction time together. That is the full picture of the dead-time ledger: the watts burned outright are only the small part — the frequency headroom that the dead-time ratio unlocks is the big one.

V. Practical Guidelines: Five Recommendations

First, compute before you compress — never jump straight to the floor. Landing at 80 ns in one step risks losing ZVS to parameter tolerance, which costs more than it saves. Start at 250 ns and step down at half and full load, checking the VSW-versus-VGS timing at each step until the design converges into the 80-150 ns range.

Second, adaptive dead time is worth the few gates of logic. A fixed dead time is optimal for at most one operating point. Detecting the VDS zero crossing in the digital controller and triggering turn-on from it lets light load and full load each claim their own dead-time floor — the established route to squeezing body-diode loss down to its physical limit.

Third, make the gate drive asymmetric. On the LLC primary, turn-on is ZVS, so turn-on loss does not care about speed: a turn-on resistor of 5-15 Ω instead dampens bridge-leg ringing and improves EMI. Turn-off is a hard event carrying magnetizing current: a turn-off resistor of 1-2 Ω pulls the gate charge out quickly and trims turn-off loss. Always pair turn-off with a -4 to -5 V negative rail to prevent dv/dt displacement-current-induced turn-on aggravated by high-temperature threshold drift (consult the datasheet).

Fourth, back light-load ZVS with Lm, not burst mode alone. Choose the magnetizing inductance at the highest value that still provides enough magnetizing energy for ZVS under light-load conditions, and treat burst mode as a supplement for light-load efficiency. If Lm is oversized, light-load ZVS collapses and the efficiency curve sags at the low end — burst mode cannot repair the conduction-loss hole underneath.

Fifth, keep the capacitive-mode protection. SiC‘s low Qrr confers strong immunity to capacitive-mode events, but immunity is not an exemption. Frequency clamping at the lower end of the modulation range and per-cycle current limiting must remain, and the bridge-leg stress under three transient classes — startup, output short, and load step — deserves dedicated verification.

VI. Vendor and Summary

The dead-time ledger of an LLC converter reduces to three layers: the direct loss of body-diode conduction, the magnetizing design space set by the ZVS energy threshold, and the frequency-scaling ceiling set by the dead-time ratio. The 650 V SiC MOSFET HXYS116N65L (650 V / 116 A / 20 mΩ, TOLL package) addresses all three layers at once: low Eoss pushes the magnetizing inductance upward, low Qrr compresses the dead-time window, and low RDS(on) contains conduction loss — with the TOLL package completing the high-density layout. As a company focused on advanced power semiconductors, HuaXuanYang Electronics (HXY Electronics) supports server and telecom power applications across data-center platforms with a full 650 V to 1200 V SiC MOSFET and SiC diode portfolio, along with selection support; the devices discussed in this article are available with datasheets and samples upon request.

Disclaimer: This article is compiled from public technical resources and HuaXuanYang Electronics product information for reference and exchange only. It does not constitute any design guarantee or commitment. Actual device selection, application, and verification should follow the latest datasheet revision and measured results. The company assumes no liability for any consequences arising from the use of this information. For reprinting, please indicate the source and contact sales@hxymos.com.